1. Field of the Invention
The present invention relates to the architecture of a semiconductor memory system and, more particularly, to a semiconductor memory circuit applied to a DRAM for outputting multiple-bit data.
2. Description of the Related Art
A DRAM with a data latch is capable of high-speed access when it outputs specified data together. The data latch is provided between a column selection gate and a sense amplifier of a memory cell and so is a transfer gate. If cell data read out of a memory cell array is transferred to the data latch through the transfer gate and then the transfer gate is turned off, data transfer between the data latch and data bus DQ connected to an output buffer through the column selection gate can be performed independently of an operation of the memory cell array.
The above circuit arrangement allows the following advantageous operation to be performed. During the sequence readout of data from the data latch, the next new data corresponding to a row (word line) is read out of a selected memory cell of the memory cell array and latched in advance in the sense amplifier. When the need arises, the transfer gate is turned on to transfer the latched data to the data latch. Thus, the time required for reading data out of a memory cell, which is usually about 60 ns, can be regarded as if it were not taken on the data bus DQ, and new row data can be read out after a lapse of a time period which is shorter than 10 ns necessary for data transfer from the sense amplifier to the data latch.
FIG. 1 is a block diagram showing a memory circuit including a DRAM with a data latch function, which is disclosed in Japanese Patent Application No. 6-74549 and based on which the present invention has been developed. Referring to FIG. 1, the memory circuit includes two DRAM cell arrays 0 and 1, and these cell arrays receive different row and column address signals to select a row (word line) and a column (bit line). More specifically, assuming that n=1, 2, 3, . . . and m=1, 2, 3, . . . (n, m=positive integer), the cell array 0 selects a column by means of a column decoder 0 and a column selection logic circuit 0 upon receiving (n+1)-bit column address signals AC00 to AC0n and selects a row upon receiving (m+1)-bit row address signals AR00 to AR0m. Similarly, the cell array 1 selects a column and a row upon receiving (n+1)-bit column address signals AC10 to AC1n and (m+1)-bit row address signals AR10 to AR1m, respectively.
The input row address signals AR00 to AR0m and AR10 to AR1m are latched at the falling edge of a RAS (row address strobe, indicates inversion) signal and supplied to row decoders 0 and 1 via row address buffers 0 and 1 and row predecoders 0 and 1 to activate a word line selected by the cell array 0 and a word line selected by the cell array 1, respectively.
The column address signals AC00 to AC0n and AC10 to AC1n are latched at the falling edge of a CAS (column address strobe, indicates inversion) signal and supplied through column address buffers 0 and 1, column predecoders 0 and 1, column decoders 0 and 1 and column selection logic circuits 0 and 1 to select a column corresponding to the cell array 0 and column corresponding to the cell array 1, respectively. The column address buffers 0 and 1 are activated when input column decoder selection signals CDSEL0 and CDSEL1 are at a high level. For example, when the signal CDSEL0 is high and the signal CDSEL1 is low, the column address buffer 0 is activated and the column address buffer 1 is deactivated. Thus, only a column corresponding to the cell array 0 is selected in response to the input column address signal.
FIG. 2 is a circuit diagram showing the main part of the memory circuit shown in FIG. 1, that is, the arrangement between the data bus DQ and cell array. The circuit includes a sense amplifier 44 for sensing the potentials of a bit line BL connected to a memory cell 451 (V.sub.PL is reference potential of plate electrode) of the cell array 0 and its complementary bit line BL. The sense amplifier 44 includes two CMOS inverters each of which is so constituted that the input of a first CMOS inverter is connected to the output of a second CMOS inverter and the output of the former is connected to the input of the latter and these inputs and outputs are connected between the bit lines BL and BL. In FIG. 2, SAP and SAN represent sense amplifier activation signals which are complementary to each other and serve as power supplies for operating the two CMOS inverters. While the signal SAP serves as a high-potential power supply in the P-channel MOS transistor, the signal SAN serves as a low-potential power supply (e.g., ground potential) in the N-channel MOS transistor.
A transfer gate 431 is provided halfway through the bit lines BL and BL to serve as a transfer switch and is controlled by an input transfer gate control signal XFER. A data latch 432 latches bit-line data transmitted from the transfer gate 431. The data latch also includes two CMOS inverters each of which is so constituted that the input of a first CMOS inverter is connected to the output of a second CMOS inverter and the output of the former is connected to the input of the latter and these inputs and outputs are connected between data lines DL and DL. To carry out the latch operation, the operating power supplies of the two CMOS inverters are connected to a high potential VC in the P-channel MOS transistors and a low potential (e.g., ground potential GND) in the N-channel MOS transistors. A column selection gate 42 is also a transfer switch for controlling the transfer of data between the data buses DQ and data lines DL and DL and in response to a column selection signal CSL.
FIGS. 3A and 3B are circuit diagrams of the main part of the memory circuit shown in FIG. 1 which includes the arrangement of the column selection gate, column decoder and column selection logic circuit. In FIG. 3A, the columns constituting the cell array 0 are divided into odd-numbered address columns and even-numbered address columns. The former columns have a sense amplifier 44, a transfer gate 431, a data latch 432 and a column selection gate 42 on the left side of the cell array 0 and are connected to the data bus DQb0, while the latter columns have a sense amplifier 44, a transfer gate 431, a data latch 432 and a column selection gate 42 on the right side thereof and are connected to the data bus DQa0. This circuit arrangement is the same as that of the cell array 1 and, in this case, the odd-numbered address columns are connected to the data bus DQb1 and the even-numbered columns are connected to the data bus DQa1 (see FIG. 3B).
The above columns include sixty-four address decode columns numbered from 0 to 63, which means that n=5 and 6-bit column address signals are input to the circuit shown in FIG. 1. Though not shown, eight pairs of columns (i.e., sixteen columns) are connected to, e.g., a single column selection signal CSL0,0, and these columns are connected to the 8-bit data buses DQ. In FIG. 3A, the transfer gate 431, data latch 432 and column selection gate 42, which are encircled with the broken line, constitute a data transmission unit for eight cells, that is, a circuit block corresponding to eight arrangements of FIG. 2, and eight pairs of columns (i.e., sixteen columns) are connected to the 8-bit data buses DQa0. This arrangement is true of FIG. 3B, and eight pairs of columns (i.e., sixteen columns) are connected to the 8-bit data buses DQa1.
A column decoder and a column selection logic circuit will now be described with reference to FIG. 3A. The column decoder 0, indicated by reference numeral 411, generates sixty-four column decode signals CS0,0 to CS0,63 upon reception of 6-bit address signals AC00 to AC05. These column decode signals are input to OR gates 4 of the column selection logic circuit, denoted by numeral 412, and the outputs thereof are supplied to the column selection gates as column selection signals CSL0,0 to CSL0,63. Thus, two adjacent columns are selected simultaneously when a specified column address signal is input.
For example, two column selection signals CSL0,1 and CSL0,2 are activated in response to an address signal corresponding to the column decode signal CS0,1. Generally, when an address signal corresponding to the i-th column decode signal is input, the i-th and the (i+1)-th column selection signals are activated, and data of eight pairs of columns corresponding to the column selection signals is read out from the data latches 432 to the data buses DQa0 (even-numbered columns of the i-th and (i+1)-th columns) and DQb0 (odd-numbered columns thereof).
The above-described column selection logic circuit is advantageously applied to a memory for storing image data having a function of making an address space correspond to the pixel array of one screen and simultaneously reading data of adjacent addresses corresponding to adjacent pixels of the pixel array. For example, it is applied to the motion compensation of a dynamic image compression device. Using the column selection logic circuit, such a special function can be easily carried out.
FIG. 4 is a conceptual view showing a screen constituted of pixels to which a column address space is applied. For easy understanding, it is assumed that the screen is constituted of 128 (=8.times.8.times.2) pixels and the column address space of the DRAM shown in FIGS. 3A and 3B is applied to such a screen. In this screen, while a0,0 to a0,63 indicate the column addresses (corresponding to AC00 to AC05) of the cell array 0, a1,0 to a1,63 represent those (corresponding to AC10 to AC15) of the cell array 1.
As illustrated in FIG. 4, the address space corresponding to one screen is achieved by forming a column address space 71 of the cell array 0 and a column address space 72 of the cell array 1 adjacent to each other. Since 8-bit data corresponds to each of the column addresses, 8-bit color information of each pixel can be applied to each column address.
Let us consider that in the screen shown in FIG. 4 the uppermost horizontal line from a0,0 to a1,7 is scanned from left to right while accessing two adjacent column addresses simultaneously. The scanning is executed according to the first to fifteenth steps as follows: a0,0 and a0,1 in STEP 1, a0,1 and a0,2 in STEP 2, . . . , and a1,6 and a1,7 in STEP 15.
An operation of the DRAM shown in FIG. 1 in the above scanning, will be described with reference to the timing chart of FIG. 5. Prior to scanning of the screen, row address signals AR00 to AR0m and AR10 to AR1m are latched at the falling edge of a RAS signal and two word lines WL corresponding thereto are activated by their respective cell arrays 0 and 1. When the word lines are activated, cell data of corresponding rows are read out to bit lines BL and BL and latched by the sense amplifiers with the sense amplifier activation signals SAP and SAN active. After that, the transfer gate control signal XFER is activated, and the latched data are transferred to the data lines DL and DL serving a pair of nodes for holding the data latched.
According to FIG. 5, when the column address a0,0 is latched at the falling edge of a CAS signal, columns corresponding to the column addresses a0,0 and a0,1 are selected by the column selection logic circuit 0 and data corresponding to the column addresses are read out to the data buses DQa0 and DQb0, respectively. The cell array 0 has only to be accessed and the cell array 1 need not be done. Therefore, only the signal CDSEL0 is set to a high level and the signal CDSEL1 is set to a low level. The data buses DQa0 and DQb0 are selected by multiplexers (a) and (b) in FIG. 1 and their data are output as DIOa and DIOb through data I/O buffers (a) and (b) (STEP 1).
The multiplexer (a) selects DQa0 when a multiplexer controlled input signal MCa is at a high level and selects DQa1 when the signal MCa is at a low level. The multiplexer (b) selects DQb0 when a multiplexer controlled input signal MCb is at a high level and selects DQb1 when the signal MCb is at a low level. In STEP 1, therefore, the signals MCa and MCb are both at a high level.
If the column address a0,1 is latched at the falling edge of the CAS signal, data corresponding to the column addresses a0,1 and a0,2 are read out to the data buses DQb0 and DQa0 and output as DIOa and DIOb through the multiplexers (a) and (b) (STEP 2).
As described above, from STEP 1 to STEP 7, two pairs of data are read out from the data latch of the cell array 0 for each of the STEPS. It is STEP 8 that we are to notice. In STEP 8, data corresponding to the column addresses a0,7 and a1,0 in FIG. 4 are read out, but the former should be read out from the data latch of the cell array 0 and the latter should be read out from the data latch of the cell array 1. Therefore, in this step, the two cell arrays can be accessed by setting both the signals CDSEL0 and CDSEL1 high, and the address signals AC00 to AC05 and AC10 to AC15 are input such that the former correspond to the column address a0,7 and the latter correspond to the column address a1,0. Then, data corresponding to the column addresses a0,8, a0,7, a1,0 and a1,1 are read out to the data buses DQa0, DQb0, DQa1 and DQb1. The multiplexer controlled input signals MCa and MCb are set to low and high levels, respectively, thereby selecting the column addresses a0,7 and a1,0 and outputting them as DIOa and DIOb (STEP 8).
From STEP 9 to STEP 15, the signals CDSEL0 and CDSEL1 are set to low and high levels, respectively, thereby to read out two pairs of data from the cell array 1. In these steps, both the signals MCa and MCb are set to a low level.
The above-described DRAM with a latch includes different data buses DQ (DQa0, DQb0, DQa1, DQb1) corresponding to the cell arrays 0 and 1 and each of the data buses has a pair of 8-bit complementary signal wirings. Therefore, the area for the data buses is so increased that high degree of integration cannot be achieved, with the result that a chip can be prevented from reducing in size.